Centers & Labs

RIKEN Advanced Institute for Computational Science

Processor Research Team

Team Leader: Kentaro Sano (Ph.D.)
Kentaro  Sano(Ph.D.)

To achieve high-performance computing with K computer, we need to use more than 80,000 computing nodes connected by a network so that they cooperate with each other by communicating data. However, the overall performance may be degraded by the big overhead for global communication and synchronization among nodes. In our research team, we develop computing accelerators to achieve large-scale computing with less performance degradation, by introducing a new parallel computing model based on localized communication and synchronization. This new approach contributes to advanced usage of K computer and design space exploration of processors and networks for future supercomputers.

Main Research Field


Related Research Fields

Informatics / Interdisciplinary science and engineering

Research Subjects

  • Acceleration mechanisms for high-performance computing with a large-scale system
  • Novel programming approach based on a data-flow computing model
  • Development and evaluation of high-performance applications based on the acceleration mechanisms and the data-flow computing model

Selected Publications

Papers with an asterisk(*) are based on research conducted outside of RIKEN.
  1. *Kentaro Sano and Satoru Yamamoto:
    "FPGA-based Scalable and Power-Efficient Fluid Simulation using Floating-Point DSP Blocks"
    IEEE Transactions on Parallel and Distributed Systems (TPDS), DOI: 10.1109/TPDS.2017.2691770, accepted (2017).
  2. *Tomohiro Ueno, Kentaro Sano, and Satoru Yamamoto:
    "Memory Bandwidth Compressor for FPGA-based High-Performance Custom Stream Computation"
    ACM Transactions on Reconfigurable Technology and Systems (TRETS), accepted (2017).
  3. *Kohei Nagasu, Kentaro Sano, Fumiya Kono, and Naohito Nakasato:
    "FPGA-based Tsunami Simulation: Performance Comparison with GPUs, and Roofline Model for Scalability Analysis"
    Journal of Parallel and Distributed Computing, DOI:10.1016/j.jpdc.2016.12.015, accepted (2016).
  4. *Kentaro Sano, Yoshiaki Hatsuda and Satoru Yamamoto:
    "Multi-FPGA Accelerator for Scalable Stencil Computation with Constant Memory-Bandwidth"
    IEEE Transactions on Parallel and Distributed Systems (TPDS), vol.25, no.3, DOI: 10.1109/TPDS.2013.51, pp.695-705 (2014).
  5. *Yoshiaki Kono, Kentaro Sano and Satoru Yamamoto:
    "Scalability Analysis of Tightly-Coupled FPGA-Cluster for Lattice Boltzmann Computation"
    Proceedings of the 22nd International Conference on Field-Programmable Logic and Applications (FPL2012), paper# W3B1, 8 pages (2012).
  6. *Kentaro Sano, Yoshiaki Hatsuda and Satoru Yamamoto:
    "Scalable Streaming-Array of Simple Soft-Processors for Stencil Computations with Constant Memory-Bandwidth"
    Proceedings of the 19th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM2011), pp.234-241 (2011).
  7. *Kentaro Sano, Wang Luzhou, Yoshiaki Hatsuda, Takanori Iizuka and Satoru Yamamoto:
    "FPGA-Array with Bandwidth-Reduction Mechanism for Scalable and Power-Efficient Numerical Simulations based on Finite Difference Methods"
    ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol.3, no.4, article no.21, DOI:10.1145/1862648.1862651, (2010).