Centers & Labs

RIKEN Center for Computational Science

Processor Research Team

Team Leader: Kentaro Sano (Ph.D.)
Kentaro  Sano(Ph.D.)

To achieve high-performance computing with a supercomputer such as K computer and supercomputer Fugaku, we need to use a huge number of computing nodes in a way that they cooperate with each other using an inter-node network to communicate among them. However, the overall performance may be degraded by the considerable overhead required for global communications and synchronization among the nodes. We are developing computing accelerators to achieve large-scale processing with less performance degradation by introducing a new parallel computing model based on a "Data-Flow" model with localized communication and synchronization. Also, we are developing data-flow accelerators where custom-computing circuits are automatically generated by a high-level synthesis compiler for each target application. Such specially customized hardware structures allow us to achieve high performance processing even for those applications which conventional CPUs are not good at handling. These research results are helping advance usage of the K computer, as well as aiding exploration of new computing models and new architectures for future supercomputers.

Main Research Field

Engineering

Related Research Fields

Informatics / Interdisciplinary science and engineering

Keywords

  • Computer Architecture
  • Parallel Processing System
  • Reconfigurable Computing
  • High-Level Synthesis
  • Hardware Algorithms

Selected Publications

Papers with an asterisk(*) are based on research conducted outside of RIKEN.
  1. Antoniette Mondigo, Tomohiro Ueno, Kentaro Sano, and Hiroyuki Takizawa.:
    "Scalability Analysis of Deeply Pipelined Tsunami Simulation with Multiple FPGAs"
    IEICE Transactions on Information and Systems(Special Section on Reconfigurable Systems), Vol.E102-D, No.5, pp.1029-1036 (2019).
  2. Antoniette Mondigo, Kentaro Sano, and Hiroyuki Takizawa.:
    "Performance Estimation of Deeply Pipelined Fluid Simulation on Multiple FPGAs with High-speed Communication Subsystem"
    Proceedings of 29th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), 4 pages (2018).
  3. *Tomohiro Ueno, Kentaro Sano, and Takashi Furusawa.:
    "Performance Analysis of Hardware-Based Numerical Data Compression on Various Data Formats"
    Proceedings of the Data Compression Conference (DCC), pp.345-354 (2018).
  4. *Kentaro Sano and Satoru Yamamoto.:
    "FPGA-based Scalable and Power-Efficient Fluid Simulation using Floating-Point DSP Blocks"
    IEEE Transactions on Parallel and Distributed Systems (TPDS), Vol.28, Issue.10, pp.2823-2837 (2017).
  5. *Tomohiro Ueno, Kentaro Sano, and Satoru Yamamoto.:
    "Bandwidth Compression of Floating-Point Numerical Data Streams for FPGA-Based High-Performance Computing"
    ACM Transactions on Reconfigurable Technology and Systems (TRETS), Vol.10, No.3, Article No.18 (2017).
  6. *Kohei Nagasu, Kentaro Sano, Fumiya Kono, and Naohito Nakasato.:
    "FPGA-based Tsunami Simulation: Performance Comparison with GPUs, and Roofline Model for Scalability Analysis"
    Journal of Parallel and Distributed Computing, Vol.106, pp.153-169 (2017).
  7. *Kentaro Sano, Yoshiaki Hatsuda and Satoru Yamamoto.:
    "Multi-FPGA Accelerator for Scalable Stencil Computation with Constant Memory-Bandwidth"
    IEEE Transactions on Parallel and Distributed Systems (TPDS), vol.25, no.3, DOI: 10.1109/TPDS.2013.51, pp.695-705 (2014).
  8. *Yoshiaki Kono, Kentaro Sano and Satoru Yamamoto.:
    "Scalability Analysis of Tightly-Coupled FPGA-Cluster for Lattice Boltzmann Computation"
    Proceedings of the 22nd International Conference on Field-Programmable Logic and Applications (FPL2012), paper# W3B1, 8 pages (2012).
  9. *Kentaro Sano, Yoshiaki Hatsuda and Satoru Yamamoto.:
    "Scalable Streaming-Array of Simple Soft-Processors for Stencil Computations with Constant Memory-Bandwidth"
    Proceedings of the 19th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM2011), pp.234-241 (2011).
  10. *Kentaro Sano, Wang Luzhou, Yoshiaki Hatsuda, Takanori Iizuka and Satoru Yamamoto.:
    "FPGA-Array with Bandwidth-Reduction Mechanism for Scalable and Power-Efficient Numerical Simulations based on Finite Difference Methods"
    ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol.3, no.4, article no.21, DOI:10.1145/1862648.1862651, (2010).

Lab Members

Principal Investigator

Kentaro Sano
Team Leader

Core Members

Tomohiro Ueno
Postdoctoral Researcher
Takaaki Miyajima
Postdoctoral Researcher
Jens Christoph Huthmann
Postdoctoral Researcher
Artur Podobas
Postdoctoral Researcher
Atsushi Koshiba
Postdoctoral Researcher

Contact information

Kobe Center for Medical Innovation
6-3-5 Minatojima-minami-machi, Chuo-ku,
Kobe, Hyogo
650-0047 Japan

Email: kentaro.sano [at] riken.jp

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