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RIKEN Center for Computational Science Processor Research Team

Team Leader: Kentaro Sano (Ph.D.)

Research Summary

Kentaro  Sano(Ph.D.)

To achieve high-performance computing with a supercomputer such as K computer and supercomputer Fugaku, we need to use a huge number of computing nodes in a way that they cooperate with each other using an inter-node network to communicate among them. However, the overall performance may be degraded by the considerable overhead required for global communications and synchronization among the nodes. We are developing computing accelerators to achieve large-scale processing with less performance degradation by introducing a new parallel computing model based on a "Data-Flow" model with localized communication and synchronization. Also, we are developing data-flow accelerators where custom-computing circuits are automatically generated by a high-level synthesis compiler for each target application. Such specially customized hardware structures allow us to achieve high performance processing even for those applications which conventional CPUs are not good at handling. These research results are helping advance usage of the K computer, as well as aiding exploration of new computing models and new architectures for future supercomputers.

Main Research Fields

  • Engineering

Related Research Fields

  • Informatics
  • Interdisciplinary Science & Engineering

Keywords

  • Computer Architecture
  • Parallel Processing System
  • Reconfigurable Computing
  • High-Level Synthesis
  • Hardware Algorithms

Selected Publications

Papers with an asterisk(*) are based on research conducted outside of RIKEN.

  • 1. Artur Podobas, Kentaro Sano, and Satoshi Matsuoka.:
    "A Survey on Coarse-Grained Reconfigurable Architectures from a Performance Perspective"
    IEEE Access, Vol.8, pp.146719-146743, DOI:10.1109/ACCESS.2020.3012084, 2020.
  • 2. Artur Podobas, Kentaro Sano, and Satoshi Matsuoka.:
    "A Template-based Framework for Exploring Coarse-Grained Reconfigurable Architectures"
    Proceedings of the 31st IEEE International Conference on Application-specific Systems,
    Architectures and Processors (ASAP),
    pp.1-8, DOI: 10.1109/ASAP49362.2020.00010, 2020.
  • 3. Antoniette Mondigo, Tomohiro Ueno, Kentaro Sano, and Hiroyuki Takizawa.:
    "Scalability Analysis of Deeply Pipelined Tsunami Simulation with Multiple FPGAs"
    IEICE Transactions on Information and Systems(Special Section on Reconfigurable Systems),
    Vol.E102-D, No.5, pp.1029-1036 (2019).
  • 4. Antoniette Mondigo, Kentaro Sano, and Hiroyuki Takizawa.:
    "Performance Estimation of Deeply Pipelined Fluid Simulation on Multiple FPGAs with High-speed Communication Subsystem"
    Proceedings of 29th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), 4 pages (2018).
  • 5. *Tomohiro Ueno, Kentaro Sano, and Takashi Furusawa.:
    "Performance Analysis of Hardware-Based Numerical Data Compression on Various Data Formats"
    Proceedings of the Data Compression Conference (DCC), pp.345-354 (2018).
  • 6. *Kentaro Sano and Satoru Yamamoto.:
    "FPGA-based Scalable and Power-Efficient Fluid Simulation using Floating-Point DSP Blocks"
    IEEE Transactions on Parallel and Distributed Systems (TPDS), Vol.28, Issue.10, pp.2823-2837 (2017).
  • 7. *Tomohiro Ueno, Kentaro Sano, and Satoru Yamamoto.:
    "Bandwidth Compression of Floating-Point Numerical Data Streams for FPGA-Based High-Performance Computing" ACM Transactions on Reconfigurable Technology and Systems (TRETS), Vol.10, No.3, Article No.18 (2017).
  • 8. *Kohei Nagasu, Kentaro Sano, Fumiya Kono, and Naohito Nakasato.:
    "FPGA-based Tsunami Simulation: Performance Comparison with GPUs, and Roofline Model for Scalability Analysis"
    Journal of Parallel and Distributed Computing, Vol.106, pp.153-169 (2017).
  • 9. *Kentaro Sano, Yoshiaki Hatsuda and Satoru Yamamoto.:
    "Multi-FPGA Accelerator for Scalable Stencil Computation with Constant Memory-Bandwidth"
    IEEE Transactions on Parallel and Distributed Systems (TPDS), vol.25, no.3, DOI: 10.1109/TPDS.2013.51, pp.695-705 (2014).
  • 10. *Kentaro Sano, Wang Luzhou, Yoshiaki Hatsuda, Takanori Iizuka and Satoru Yamamoto.:
    "FPGA-Array with Bandwidth-Reduction Mechanism for Scalable and Power-Efficient Numerical Simulations based on Finite Difference Methods"
    ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol.3, no.4, article no.21, DOI:10.1145/1862648.1862651, (2010).

Related Links

Lab Members

Principal investigator

Kentaro Sano
Team Leader

Core members

Tomohiro Ueno
Postdoctoral Researcher
Boma Anantasatya Adhi
Postdoctoral Researcher
Carlos Cesar Cortes Torres
Postdoctoral Researcher
Masahiro Iida
Senior Visiting Scientist
Yasushi Inoguchi
Senior Visiting Scientist
Yuichiro Shibata
Senior Visiting Scientist
Hiroyuki Takizawa
Senior Visiting Scientist
Masanori Hariyama
Senior Visiting Scientist
kazuya Tanigawa
Visiting Scientist
Hasitha Muthumala Waidyasooriya
Visiting Scientist
Ryohei Kobayashi
Visiting Scientist
Norihisa Fujita
Visiting Scientist
Hideki Takase
Visiting Scientist

Careers

Position Deadline
Seeking a Research Scientist or Postdoctoral Researcher (R-CCS2105) Open until filled
Seeking a Research Scientist or Postdoctoral Researcher (R-CCS2022) Open until filled

Contact Information

Kobe Center for Medical Innovation
6-3-5 Minatojima-minami-machi, Chuo-ku,
Kobe, Hyogo
650-0047 Japan
Email: kentaro.sano [at] riken.jp

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